Please refer to FIG. 1, which is a circuit diagram showing a conventional memory cell fuse circuit according to the prior art. In FIG. 1, the memory cell fuse circuit 1 includes a PMOS transistor M1, a capacitor CL, a NMOS transistor M2, a fuse latch 10, a NOR gate NR1, a NMOS transistor M3, and a fuse cell M4. The fuse latch 10 includes two inverters IV1 and IV2 connected reversely in parallel to each other.
In the memory cell fuse circuit 1, the PMOS transistor M1 has a source electrically connected to a voltage source VDD, a gate electrically connected to reset signal FRESETB, a drain electrically connected to one end of the capacitor CL and the input of the inverter IV1. The NMOS transistor M2 has a drain electrically connected to the fuse cell M4, a gate electrically connected to a bias signal BIAS, and a source electrically connected to the output of the inverter IV2. The NOR gate NR1 has a first input electrically connected to a control signal FPGMB, a second input electrically connected to the output of the inverter IV1 and the input of the inverter IV2, an output electrically connected to the gate of the NMOS transistor M3. The drain of the NMOS transistor M3 is electrically connected to the fuse cell M4. The control terminal of the fuse cell M4 is electrically connected to a word line signal FWL.
FIG. 2 is a diagram showing the signals in the memory cell fuse circuit of FIG. 1. With reference to FIGS. 1 & 2, the operation principles of the memory cell fuse circuit 1 are described as follows. When the voltage source VDD is high, an external signal POR (not shown in FIG. 1) is high. The reset signal FRESETB is low and the PMOS transistor M1 is turned on. The capacitor CL is precharged so that the node FD reaches a high level VDD. The bias signal BIAS rises and the word line signal FWL rises. One terminal of the fuse cell M4 is connected to ground GND. The memory cell fuse circuit 1 is in the reading mode to read the values of the cell M4.
Based on the digits of the memory, the memory has the corresponding number of the memory cell fuse circuits 1. By the above operations toward all of the memory cell fuse circuits, the whole configuration memory can be read completely, so as to confirm the initial condition of the memory.
In the memory cell fuse circuit, there exists one reference cell fuse circuit and the others are normal cell fuse circuits. Generally, the cell current of the normal cell fuse circuit is more than that of the reference cell fuse circuit, and the fuse latch of the reference cell fuse circuit is stronger than that of the normal cell fuse circuit. Therefore, it is certain that the reference cell fuse circuit swaps slower than the normal cell fuse circuit.
However, for the factors of the manufacturing process, the transistor of the fuse cell will have a threshold voltage (VT) distribution as shown in FIG. 3. If the VT value of the fuse cell transistor in the reference cell fuse circuit is smaller, i.e. at the left of the distribution curve of FIG. 3, the normal cell fuse circuit with a larger VT value, i.e. at the right of the distribution curve of FIG. 3, will be regarded as fail when the word line signal FWL turns off the normal cell fuse circuit.